Data processing systems often require that peripheral devices, terminals or a multiple of computers communicate. In a high performance data processing system, the intercommunications between system components is critical in gaining the high performance required. An example of a high performance system commonly used is the telecommunications system.
U.S. Pat. No. 4,256,926 is an example of a microcontrolled telecommunications switching system that includes distributed control through distributed microprocessors where the microprocessors include buffers that provide for the communications required between the microprocessors.
U.S. Pat. No. 4,119,803 discloses a telephone exchange switching system that is controlled by a pair of control units which, through a centralized mechanism, include multiple registers for controlling traffic and a dialog portion that provides control and information communications with the telephone exchange equipment.
U.S. Pat. No. 4,412,282 discloses a microprocessor controlled telephone switching circuit that provides for increased reliability through data and address parity circuits.
U.S. Pat. No. 4,580,011 is a distributed processing telephone switching system that includes a master control microprocessor that in turn controls several special function microprocessors.
The difference between a telecommunications circuit and the common data processing intercommunication circuit is that in a data processing system the number of terminals for communication are fewer and that data throughput required for the data processing system communication is generally higher. However, dynamic interconnectibility is still a requirement. Therefore, different techniques are provided for communicating between one element of the data processing system and another. An example of this is illustrated in U.S. Pat. No. 4,264,782 where a host processor is communicating to several terminals through a data communication network. In this system, communications can be encrypted but are still controlled by the host CPU. When the host CPU is master, the terminals become slaves and all control of the communications over the data communications network is then controlled by the host CPU. This can be a bottleneck when the data processing systems include several autonomous elements requiring communications.
U.S. Pat. No. 4,551,831 is another example of a data processing communications network that illustrates a multiplex switch used to control several channels. A central CPU controls the multiplex switch. A further illustration of data processing element communications is illustrated in U.S. Pat. No. 4,710,868 that illustrates the interconnection of several workstations to a central memory. The workstations access the central memory through a two level switch that provides for virtual to real address translation, as well as switching.
Many high performance data processing communications systems require that several data processing elements communicate simultaneously with each other. This capability is provided by using a cross point switch. An example of a cross point switch implementation is illustrated in U.S. Pat. No. 4,539,564. This is compared with a single information bus that provides only a single channel of communication at any one time. In a typical configuration, a cross point switch will provide the capability for any terminal to talk with any other nonbusy terminal on the system and further provide for simultaneous communications between several terminal pairs. Traditionally this is accomplished by a terminal requesting access to the cross point switch through a central switch controller to determine if the receiving terminal can receive a transmission from the originating terminal. Upon receiving a status signal indicating that such communications can be completed, the cross point switch is commanded to make the connection between the transmitting terminal and the receiving terminal in order that the two terminals can exchange information. When the communication is to be ended, the originating terminal traditionally signals the central controller of the cross point switch to disconnect the receiving terminal.
It is an object of the present invention to provide an intelligent mechanism for regulating the intercommunication between elements in a data processing system by monitoring their communications to determine when a change in the communications system is to be made. This objective is accomplished by monitoring the transmissions between the two system elements.
U.S. Pat. No. 4,539,564 that illustrates an embodiment of a cross point type switch which discloses monitors inputs and outputs. However, this monitoring is only provided for maintenance to determine when error conditions occur and the sources of these error conditions. Likewise, IBM Technical Disclosure Bulletin, Vol. 31, No. 1, June, 1988, entitled "Cross Point Switch Tracer", also includes a maintenance circuit to monitor and time stamp communications through a cross point type switch. Neither of these references, nor the other references detailed above, describe any mechanism in which the communications are monitored in order to regulate the communications over an information bus.